High speed composite p-channel Si/SiGe heterostructure for field effect devices

ABSTRACT

A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.

FIELD OF THE INVENTION

[0001] This invention relates to a silicon and silicon germanium basedmaterials system and more specifically, to a novel epitaxial fieldeffect transistor structure capable of high-speed low-noise, microwave,submillimeter-wave and millimeter-wave applications. Preferably, theepitaxial field effect transistor structure includes a high performancestrained p-channel incorporating silicon, germanium, and silicongermanium layers to form a modulation-doped heterostructure.

BACKGROUND OF THE INVENTION

[0002] In high speed and low noise device applications, the focus hasbeen on designing and fabricating high electron mobility transistors(HFMTs) or modulation-doped field effect transistors (MODFETs) wherecarrier (eg. electrons, holes) conduction occurs in an undoped channellayer such that the carrier mobility is not limited by impurityscattering and high carrier mobility is achieved. In general, these highspeed electronic devices are often used as low-noise amplifiers, poweramplifiers, satellite receivers and transmitters operating in themicrowave and rf regime, and the material of choice is usually thefaster but more expensive III-V (e.g. GaAs) materials system andtechnology. A complicated and costly III-V materials technology is notvery desirable in the semiconductor industry whereas a less-expensiveSiGe materials system which is fully compatible with present Sitechnology is more desirable and far easier to integrate with existingSi-CMOS device technology.

[0003] One example of a material system compatible with Si technology isdescribed in U.S. Pat. No. 5,019,882 which issued on May 28, 1991 to P.M. Solomon entitled “Germanium Channel Silicon MOSFET” and assigned tothe assignee herein. In U.S. Pat. No. 5,019,882, a channel havingimproved carrier mobility comprises an alloy layer of silicon andgermanium which is grown above a silicon substrate. The alloy layer iskept thin enough for proper pseudomorphic dislocation free growth. Alayer of silicon is formed over the alloy layer and is oxidizedpartially through to form a dielectric layer. A gate region is formedover the silicon dioxide.

[0004] A second example of a high performance SiGe device structurecompatible with Si technology, is described in U.S. Pat. No. 5,534,713which issued on Jul. 9, 1996 to K. E. Ismail entitled “ComplementaryMetal-Oxide Semiconductor Transistor Logic Using Strained Si/SiGeHeterostructure Layers” and assigned to the assignee herein. In U.S.Pat. No. 5,534,713 a silicon CMOS transistor structure is describedutilizing a buried SiGe channel under compressive strain with enhancedhole mobility for a p-channel device, and a buried Si channel undertensile strain with enhanced electron mobility for an n-channel devicefabricated on a strained Si/SiGe heterostructure design. Further in U.S.Pat. No. 5,534,713 the proposed compressively-strained SiGe layerserving as a p-channel for the p-channel field effect transistor isdescribed as having a composition of germanium in the range from 50 to100% and with a preferred composition of 80%. Thus far, prototype SiGep-channel MODFETs utilizing this channel design and composition at theIBM Corporation have yielded hole mobilities only up to 1,000 cm²/Vs atroom temperature. Consequently, in order to achieve an even higher holemobility of greater than 1,000 cm²/Vs, a p-channel design with acomposite or dual layer structure composed of a Ge layer (of 15-20 Åthick) together with a SiGe layer of 70-80% Ge (of 70-100 Å thick) ispresented as the optimum p-channel structure to produce a higher holemobility in a SiGe materials system.

SUMMARY OF THE INVENTION

[0005] In accordance with the present invention, a silicon and silicongermanium based epitaxial structure for a p-type field-effect transistorthat utilizes a composite or a dual layer structure of substantiallypure Ge and a SiGe layer in a p-channel region is described for forminga p-channel device comprising a semiconductor substrate, a first layerof relaxed Si_(1−x)Ge_(x) formed epitaxially on the substrate where theGe fraction x is in the range from 0.35 to 0.5, a second layer of pdoped Si_(1−x)Ge_(x) formed epitaxially on the first layer, a thirdlayer of undoped Si formed epitaxially on the second layer whereby theSi layer is under tensile strain and remains commensurate with respectto the top of the first relaxed Si_(1−x)Ge_(x) layer, a fourth layer ofundoped Si_(1−x)Ge_(x) formed epitaxially on the third layer, a fifthlayer of undoped Ge formed expitaxially on the fourth layer whereby theGe layer is under compressive strain and remains commensurate withrespect to the top of the first relaxed Si_(1−x)Ge_(w) layer, a sixthlayer of undoped Si_(1−y)Ge_(y) formed epitaxially on the fifth layerwhere the Ge fraction w is in the range from 0.5 to less than 1.00 andwhere w-x>0.2 whereby the Si_(1−w)Ge_(w) layer is under compressivestrain, and a seventh layer of undoped Si_(1−x)Ge_(x) formed epitaxiallyon the fifth layer. A metal layer alone to form a Schottky barrier or adielectric and metal layer may be formed and patterned over the seventhlayer to form the gate of the p-channel field effect transistor whilethe drain and source regions may be formed by forming p regions oneither side of the gate in the layered structure. This layered structuredesign forms a modulation-doped heterostructure whereby the supply layeror the second p-doped Si_(1−x)Ge_(x) layer is located below the activecomposite channel of layers of five and six. Furthermore, in thislayered device structure, the spacer layer which separate the activechannel from the supply layer employs a dual layer comprising the thirdlayer of undoped Si and the fourth layer of undoped Si_(1−x)Ge_(x).

[0006] The invention further provides a method for forming and ap-channel field effect transistor having increased hole mobility in itschannel comprising a semiconductor substrate, a first layer of relaxedSi_(1−x)Ge_(x) formed epitaxially on the substrate where x is in therange from 0.35 to 0.5, a second layer of p doped Si_(1−x)Ge_(x) formedepitaxially on the first layer, a third layer of undoped Si_(1−x)Ge_(x)formed epitaxially on the second layer, a fourth layer of undoped Geformed epitaxially on the third layer whereby the Ge layer iscommensurate with respect to the top of the first relaxed Si_(1−w)Ge_(w)layer, a fifth layer of undoped Si_(1−y)Ge_(y) formed epitaxially on thefourth layer where the Ge fraction w is in the range from 0.5 to lessthan 1.00 and the fifth Si_(1−w)Ge_(w) layer is under compressivestrain, and a sixth layer of undoped Si_(1−x)Ge_(x) formed epitaxiallyon the fifth layer. This layered structure design describes amodulation-doped heterostructure whereby the supply layer or p-dopedSi_(1−x)Ge_(x) second layer is separated from the active compositechannel in the fourth and fifth layers by a single spacer third layerdesign of Si or Si_(1−x)Ge_(x).

[0007] The invention further provides a method and a p-channel fieldeffect transistor having increased hole mobility in its channelcomprising a semiconductor substrate, a first layer of relaxedSi_(1−x)Ge_(x) formed epitaxially on the substrate where x is in therange from 0.35 to 0.5, a second layer of undoped Ge formed epitaxiallyon the top of the first layer whereby the Ge layer is commensurate withrespect to the top of the first relaxed Si_(1−x)Ge_(x) layer, a thirdlayer of undoped Si_(1−w)Ge_(w) formed epitaxially on the second layerwhere the Ge fraction w is in the range from 0.5 to less than 1.00 andthe third Si_(1−w)Ge_(w) layer is under compressive strain, a fourthlayer of undoped Si_(1−x)Ge_(x) formed epitaxially on the third layer,and a fifth layer of p-doped Si_(1−x)Ge_(x) formed epitaxially on thefourth layer. This layered structure design describes a modulation-dopedheterostructure whereby the supply layer or the fifth layer of p-dopedSi_(1−x)Ge_(x) is located above the active composite channel comprisingthe second and third layer. Likewise, the supply layer or the fifthlayer of p-doped Si_(1−x)Ge_(x) can be further separated above theactive composite channel of the second and third layer with the additionof a Si spacer layer between the third and fourth layer, oralternatively between the fourth and fifth layer.

[0008] The invention further provides a method and a structure for arelaxed (greater than 90%) Si_(1−x)Ge_(x) buffer layer comprising asemiconductor substrate, a first layer of partially relaxed (less than50%) Si_(1−x)Ge_(x) formed epitaxially by stepwise grading (or lineargrading) where the Ge content of the layers is increased in a stepwisefashion (or in a linear fashion) starting on a substrate and x is in therange of 0.1 to 0.9, a second layer of Si_(1−y)Ge_(y) formed epitaxiallyon the first layer where y=x+z and z is in the range from 0.01 to 0.1which serves to “over relax” the second layer to an equivalentcomposition and having a lattice spacing corresponding to a compositiongreater than x, and a third layer of Si_(1−x)Ge_(x) formed epitaxiallyon the second layer whereby Si_(1−x)Ge_(x) layer is now more relaxed ascompared to the original, partially relaxed Si_(1−x)Ge_(x) first layer.The extent of additional relaxation due to this “over shoot” secondlayer of Si_(1−y)Ge_(y) does depend on the thickness of this secondlayer which in turn is limited by its critical thickness on the initialpartially relaxed Si_(1−x)Ge_(x) first layer.

[0009] The invention further provides a p-type field-effect transistorcan be fabricated on one of the previously described layer structureswhere the conducting channel of the device is composed of a composite ordual layer structure comprising a substantially pure Ge layer and a SiGelayer. The field-effect transistor is isolated by regions created byselectively removing the top barrier layer, the conducting dual layerchannel, the undoped spacer regions and the p-type doping region suchthat a two-dimensional channel is formed only within an isolated activedevice region. A gate electrode consisting of a conducting stripe may beformed directly on the wafer surface above the active device region, andsource and drain electrodes may be formed by making Ohmic contact to theconducting dual layer channel on either side of the gate electrodewithin the active device region.

[0010] It is an object of this invention to provide a p-typemodulation-doped field-effect transistor (MODFET) that is fabricated ona composite or dual-layer structure comprising substantially pure Gelayer and a SiGe layer.

[0011] It is an object of the invention to provide a layered structurewhich allows for p-channel field effect transistors to be formed havinga channel with a unique composition profile as a function of depth.

[0012] It is a further object of the invention to provide a p-channeldevice where the active channel is a composite or dual layer structurecomposed of a thin Ge layer together with a SiGe layer.

[0013] It is a further object of the invention to provide p-channeldevices where the composite channel structure takes advantage of thehigher compressive strain with the benefits of higher carrier mobilityand a higher barrier or a deeper confining channel for hole carriers ascompared to a channel with a single SiGe layer.

[0014] It is a further object of the invention to provide a buriedcomposite channel of a Ge layer with a SiGe layer under compressivestrain for higher carrier mobility in a p-channel device.

[0015] It is a further object of the invention to provide a p-channeldevice where the spacer layer is a composite or dual layer designcomposed of a thin Si layer together with a SiGe layer.

[0016] It is a further object of the invention to provide a layeredstructure and process for making where a desired relaxed SiGe layer canbe more fully relaxed by the addition of one or more over shoot layersin the grade-up composition of the SiGe buffer structure.

[0017] It is a further object of the invention to provide a p-MODFETwith higher hole mobility compared to the prior art, such as bulk Sip-MOSFETs and single-channel SiGe p-MODFETs.

[0018] It is a further object of the invention to provide a p-MODFETwith enhanced high-frequency operation compared to bulk Si p-MOSFETs orcompared to single-channel SiGe p-MODFETs due to higher carriermobility.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] These and other features, objects, and advantages of the presentinvention will become apparent upon consideration of the followingdetailed description of the invention when read in conjunction with thedrawing in which:

[0020]FIG. 1 is a cross section view of a layered structure illustratingone embodiment of the invention.

[0021]FIG. 2 is a cross-sectional TEM of a fabricated sampleillustrating the complete layered structure of the embodiment of theinvention shown in FIG. 1.

[0022]FIG. 3 is a SIMS graph showing the Ge concentration versus depthfor the fabricated sample structure shown in FIG. 2 illustrating thepreferred Ge compositional layered structure of the embodiment of theinvention.

[0023]FIG. 4 is an expanded SIMS view of the top part of FIG. 3 to adepth of about 1000 Å showing the B and Ge concentration for themodulation-doped device region.

[0024]FIG. 5 shows the X-ray rocking curves for the (004) reflectionfrom the relaxed fabricated layered structure shown in FIG. 2.

[0025]FIG. 6 is a detailed cross-sectional TEM of the upper deviceregion of the fabricated sample structure shown in FIG. 2 illustratingthe composite p-channel modulation-doped device structure of theembodiment of the invention.

[0026]FIG. 7 is a detailed cross-sectional TEM of a channel region of adevice structure when fabricated on a less relaxed buffer as compared tothe layered structure of FIG. 1 illustrating the presence of stackingfaults in the active channel.

[0027]FIG. 8 is a graph of the measured hole mobility versus temperaturein Kelvin (K) from Hall measurements comparing the hole mobilitybehavior of a high quality p-channel device structure shown in FIG. 5with a poor quality p-channel device structure filled with stackingfaults shown in FIG. 6.

[0028]FIG. 9 is a cross section view of a layered structure illustratinga second embodiment of the invention.

[0029]FIG. 10 is a plan-view diagram of a field-effect transistor.

[0030]FIG. 11 is a cross-section view along the line 12-12 of FIG. 11showing the composite p-channel layer structure.

[0031]FIG. 12 is a cross-section view of an insulating gate field-effecttransistor on a composite p-channel layer structure.

[0032]FIG. 13 is an SEM micrograph of a portion of a completed,self-aligned MODFET fabricated on a composite p-channel layer structureshown in FIGS. 11 and 12.

[0033]FIGS. 14 and 15 are plots of data points of the forward currentgain and maximum unilateral gain versus frequency measured with V_(ds)equal to −0.6V and −1.5V, respectively, of a p-MODFET fabricated with acomposite p-channel layer structure similar to the MODFET shownpartially in FIG. 13.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Referring to the drawing, and in particular to FIG. 1, a crosssection view of a layered structure 10 for a composite p-channelmodulation-doped SiGe heterostructure is shown to illustrate theembodiment of the invention. Layers 12-18 are epitaxially grown on asingle crystal semiconductor substrate 11 which may be Si, SiGe, Ge,SiC, GaAs, SOS, SOI, Bond and Etch back Silicon On Insulator (BESOI),etc. using an epitaxial growth technique such as ultra high vacuumchemical vapor depositon (UHV-CVD), molecular beam epitaxy (MBE), orrapid thermal chemical vapor deposition (RTCVD). For a description ofUHV-CVD methods for growing epitaxial Si and Si,,Ge, films on a siliconsubstrate, reference is made to U.S. Pat. No. 5,298,452 by B. S.Meyerson which issued Mar. 29, 1994 entitled “Method and Apparatus forLow Temperature, Low Pressure Chemical Vapor Deposition of EpitaxialSilicon Layers” which is incorporated herein by reference.

[0035] An illustration of a preferred layered structure 20 is shown inFIG. 2 which is the lower portion of layered structure 10 shown inFIG. 1. FIG. 2 shows a cross-sectional TEM view of a fabricated layeredstructure 20 comprising layers 12A, 12B, 12C, and 13-18 grown on apreferred silicon substrate 31. The corresponding Ge compositionalprofile of SiGe layered structure 20 of FIG. 2 as measured by secondaryion mass spectroscopy (SIMS) is shown in FIG. 3. In FIG. 3, the ordinaterespresents Ge concentration in atomic percent and the abscissarepresents approximate depth in microns. In FIG. 3, curve portions21′-27′, 12B′ and 12C′ correspond to the Ge concentration in layers21-27, 12B and 12C shown in FIG. 2.

[0036]FIG. 4 is an expanded view of just the top part of FIG. 3 showingthe device region only. In FIG. 3A, the ordinate on the right siderepresents Ge concentration in atomic percent and the abscissarepresents approximate depth in angstroms. Curve 37 shows the Geconcentration as a function of approximate depth. In FIG. 4, theordinate on the left side represents boron concentration in atoms/cc andcurve 39 shows the boron concentration as a function of approximatedepth.

[0037] The first epitaxial layer, described as layer 12A in FIGS. 1 and2, of a relaxed Si_(1−x)Ge_(x) formed on the upper surface of substrate11, 31 is comprised of a step-graded Ge compositional layer structurecomprising layers 21-27. Layers 21-27 have a preferred profile shown inFIG. 3 where the strain has been relieved in the buffer layers 21-27 orbelow in substrate 11, 31 via a modified Frank Read source as amechanism to generate new dislocations 33 which is shown in FIG. 2 anddescribed in U.S. Pat. No. 5,659,187 which issued on Aug. 19, 1997 to F.K. Legoues and B. S. Meyerson, and herein incorporated by reference.

[0038] Buffer layer 12 comprises layers 12A, 12B and 12C and may beinitially undoped, relaxed, and have a Ge composition at interface 19between layers 12 and 13 in the range from about 30% to about 50% with apreferred value of about 35%.

[0039] The design of layer 12 is actually made of a startingSi_(1−x)Ge_(x) layer 12A of a graded Ge composition formed over a Sisubstrate 11, 31 followed by an overshoot layer of Si_(1−y)Ge_(y) layer12B where y=x+z and z is in the range of 0.01 to 0.1 with a preferredvalue of 0.05 formed over layer 12A, and finally by a more relaxedSi_(1−x)Ge_(x)′, layer 12C, formed over layer 12B. Basically, theovershoot layer 12B functions to ensure a high degree of relaxation,i.e. >90% for the top Si_(1−x)Ge_(x)′ surface layer 12C at interface 19.In the preferred case of achieving a fully relaxed Si_(0.65)Ge_(0.35)layer 12C, it is desirable to use an overshoot layer 12B ofSi_(0.60)Ge_(0.40) as shown in FIG. 3 by curve portion 12B′ with respectto curve portions 21′-27′. In relaxed Si_(1−x)Ge_(x)′ layer 12C, thein-plane lattice parameter, a_(SiGe)(x), is given by equation (1):

a _(SiGe)(x)=a _(Si)+(a _(Ge) −a _(Si))x  (1)

[0040] where x is the Ge content and 1−x is the Si content and a_(Si)and a_(Ge) corresponds to the lattice constant for Si and Gerespectively, and consequently in the preferred case when the topSi_(0.65)Ge_(0.35) surface layer is >90% relaxed, layer 12C would have alattice constant which is greater than 4.956 Å. Structurely, layer 12serves to relax the strain caused by the lattice mismatch between thetop surface or interface 19 of relaxed layer 12C and the underlying Sisubstrate 11, 31 where there is a 4.2% lattice misfit as Ge has alattice spacing of 1.04 times larger than the lattice spacing of singlecrystal Si. The buffer thickness of layer 12 can range from 0.2 to 5 μmbut the preferred thickness is about 2.5 μm with a Ge compositionalprofile increasing from x=0 in a preferred stepwise fashion (compared toa continuous, linearly graded fashion) to a value in the range fromx=0.10 to 1.0 with a preferred value of x=0.35 using a stepwise increaseof 0.05 Ge per incremental layer as shown in FIG. 2 by layers 21-27 andin FIG. 3 by curve portions 21′-27′.

[0041] To assess the ability of layer 12 to achieve a fully relaxedSi_(0.65)Ge_(0.35) buffer, high resolution x-ray diffraction (XRD) wasused to characterize the fabricated sample structure of FIG. 2. Themeasured spectrum is shown by x-ray rocking curve 62 for the (004)reflection in FIG. 5 which after analysis indicates that the upper partof SiGe buffer layer 12C at interface 19 is at a lattice parametercorresponding to a Ge compositional value of x=0.35 with a strainrelaxation of about 95% with respect to the underlying Si substrate 31.In FIG. 5, the ordinate represents intensity in arbitrary units and theabscissa represents Bragg angle. Curve portion 63 of curve 62 shows themeasured diffraction spectra for the composite hole channel 16 and 17.Curve portion 64 of curve 62 shows the measured diffraction spectra forthe step graded layer 12. Curve portion 65 of curve 62 shows themeasured diffraction spectra for the overshoot layer 12B. Curve portion66 of curve 62 shows the measured diffraction spectra for substrate 11.

[0042] The preferred method of growing silicon and silicon containingfilms, i.e. Si:B, Si:P, SiGe, SiGe:B, SiGe:P, SiGeC, SiGeC:B, SiGeC:P isthe UHV-CVD process as described in U.S. Pat. No. 5,298,452 by B. S.Meyerson mentioned above. A UHV-CVD reactor suitable for growing theabove-mentioned silicon and silicon containing films is available fromLeybold-Heraeus Co. in Germany, Epigress in Sweden, and CVD EquipmentCorp. in Ronkonkoma, N.Y., USA.

[0043] In layered structure 10 for a composite p-channelmodulation-doped SiGe heterostructure, a p-doped relaxed SiGe layer 13as shown in FIG. 1 is first formed over layer 12C to function as thedonor or supply layer beneath an active channel. Layer 13 may have athickness in the range from 1 to 20 nm with a preferred thickness in therange from 4 to 5 nm and should have an electrically active donor dosein the range from 1 to 3×10¹² cm⁻². The p-type dopant of layer 13 may beincorporated in SiGe layer 13 by doping with different flows of B₂H₆during epitaxial growth of layer 13. An example of a preferred borondopant profile for SiGe layer 13 is shown in FIG. 3A with an integrateddose of 1.5×10¹² boron/cm². An undoped strained Si layer 14 isepitaxially formed above p-doped layer 13 as a spacer layer. Layer 14functions to separate the dopants in layer 13 from the active channellayers 16 and 17 to be formed above. The thickness of layer 14 shouldremain below the critical thickness of a silicon layer with respect tothe lattice spacing at interface 19 of relaxed layer 12. The preferredthickness of layer 13 is in the range from 1 to 2 nm in the case whenlayer 12 at interface 19 is a relaxed Si_(0.65)Ge_(0.35) layer.

[0044] Next, a thin relaxed undoped SiGe layer 15 is epitaxially grownover layer 14 and similar to layer 14, functions as a spacer layer tofurther separate the dopants in layer 13 from the above compositechannel 33 comprising layers 16 and 17 in order to maintain a high holemobility in layers 16 and 17. The thickness of layer 15 may range from 0to 10 nm, with the preferred thickness in the range from 4 to 5 nm. Acompressively-strained Ge layer 16 is epitaxially grown above layer 15which functions as the first part of a composite p-channel 33 forp-channel field effect transistors. For a detailed description of aUHV-CVD method for growing an epitaxial Ge film on a silicon substrate,reference is made to U.S. Pat. No. 5,259,918 by S. Akbar, J. O. Chu, andB Cunningham which issued Nov. 9, 1993 entitled “Heteroepitaxial Growthof Germanium on Silicon by UHV/CVD” which is incorporated herein byreference. In order for layer 16 to be an effective component in thecomposite p-channel 33, the epitaxial Ge must be of device quality layervoid of structural defects, e.g. stacking faults and any interfaceroughness problems between layers 16 and 17. For example, in thepreferred case when layer 12C is a relaxed Si_(0.65)Ge_(0.35) layer atinterface 19, the thickness of Ge layer 16 may be in the range from 0 to25 Angstroms with a preferred thickness of 20 Angstroms as shown in FIG.6. It should be noted that to maintain a layer thickness of 20 Angstromsfor Ge layer 16, it is critical that layer 12 at interface 19 must beequal to or at least equivalent in lattice spacing to a 90% relaxedSi_(0.65)Ge_(0.35) buffer. Otherwise, stacking faults will occur in Gelayer 16 in the case when grown on a smaller lattice spacingcorresponding to a less relaxed or lower Ge content buffer layer 12 atinterface 19 as shown in FIG. 7.

[0045]FIG. 6 shows Ge layer 16 with stacking faults in the range from10⁴ to 10⁶ defects/cm². The stacking faults originating in Ge layer 16may extend upwards into Si12:15 PM_(1−w)Ge_(w) layer 17. Si_(1−w)Ge_(w)layer 17 also should have stacking faults in the range from 10⁴ to 10⁶defects/cm². In FIG. 6, the smoothness of the upper surface of layer 17at interface 42 is shown. Stacking faults are reduced to below 10⁶defects/cm² by the 90% relaxation of layer 12 at interface 19. Thepercent of relaxation of a layer can be determined by measuring thelattice constant such as by X-ray diffraction (XRD) as mentioned above.

[0046]FIG. 7 shows layers 12-18 similar to FIG. 6, but in FIG. 7 layer12 and specifically at interface 19 the lattice constant corresponded toa relaxation of less than 90% resulting in stacking faults of above 10⁶defects/cm² and typically in the range from 10⁶ to 10⁸ defects/cm² whichare undesireable for electronic devices.

[0047] Above layer 16, a compressively strained SiGe layer 17 isepitaxially grown which will serve as the second part of compositechannel 33 of a p-channel field effect transistor. The Ge compositionfor SiGe layer 17 may range from 50% to <100%, and the preferredcomposition is 80% with a thickness ranging from 40 to 100 Angstroms.Alternatively, SiGe layer 17 may have the germanium content gradedwithin SiGe layer 17, decreasing from, for example, 0.95 Ge at the lowerportion of the layer nearer the Ge layer 16 to about 0.50 Ge at theupper part of SiGe layer 17.

[0048] Above layer 17, a SiGe cap layer 18 is grown having the preferredGe composition the same as that of layer 12C at interface 19 andfunctions to separate p-channel 33 from the surface and to confine thehole carriers in layers 16 and 17. The thickness for layer 17 may rangefrom 2 to 20 nm, with the preferred thickness in the range from 10 to 15nm. Layers 13, 15, and 18 may have the same composition of silicon andgermanium to provide the same lattice spacing where the Ge content maybe in the range from 20 to 50% with a preferred value of 35% in the casewhen layer 12C at interface 19 has a lattice spacing equalivalent to arelaxed Si_(0.65)Ge_(0.35) buffer layer.

[0049] The channel confinement of holes and its enhanced transportmobility is a result of the higher compressive strain in the compositechannel structure having two high Ge content layers with respect to therelaxed buffer layer of layer 12 at interface 19 arising from the 4.2%larger lattice constant for pure Ge relative to Si. The structuralability to create and enhance the compressive strain in the SiGe or Gechannel layers formed on the relaxed SiGe buffer of layer 12 cansignificantly alter the conduction and valence bands of the p-channellayers of 16 and 17. Moreover, an important parameter for the design ofthe p-channel modulation-doped heterostructure is the valence-bandoffset (ΔE_(v)) of the compressively strained Si_(1−x)Ge_(x) or Gechannel layer relative to the relaxed Si_(1−x′)Ge_(x′) epilayer of layer12, and is given by equation (2):

ΔE _(v)=(0.74−0.53x′)x(eV)  (2)

[0050] where x′ is the Ge content of the relaxed SiGe epilayer of layer12 and x is the Ge content in the hole channel. This formulation isreported in a publication by R. People and J. C. Bean entitled “Bandalignments of coherently strained Ge_(x)Si_(1−x)/Si heterostructures on<001>Ge_(y)Si_(1−y) substrates”, Appl. Phys. Lett. 48 (8), Feb. 28,1986, pp538-540 which is incorporated herein by reference. Morespecifically, the valence band discontinuity (ΔE_(v)) for layer 17 whenit is a Si_(0.2)Ge_(0.8) channel formed over a relaxedSi_(0.65)Ge_(0.35) of layer 12 would be 443 meV, and in the case of apure Ge channel of layer 16 an even larger band offset of 554 meV isgenerated in the hole or valance band which would essentially produce adeeper quantum well or a more effective barrier for hole confinement.Importantly, the compressive strain in the SiGe or Ge layer also servesto split the valence band into the heavy hole and light-hole bandswhereby the hole transport in the upper valence band with the lighterhole mass for carrier transport along the strained channel will resultin enhanced hole mobilites that could be significantly higher asdescribed below than in Si p-channel field effect transistors whichtypically has a mobility of about 75 cm²/Vs as reported in a publicationby M. Rodder et at. entitled “A 1.2V, 0.1 μm Gate Length CMOSTechnology: Design and Process Issues”, IEDM 98-623. Consequently, themeasured hole mobilities in the occupied hole band for the compositechannel structure are in the range from 900 to 1400 cm²/Vs at 300K andin the range from 5000 to 10000 cm²/Vs at 20K for the case when layer 17is a Si_(0.2)Ge_(0.8) channel with a thickness in the range from 7 to 8nm and layer 16 is a Ge channel with a thickness in the range from 1.5to 2.0 nm.

[0051] Furthermore, FIG. 8, curve 71, shows the measured two-dimensionalhole gases (2DHG) hole mobility behavior as a function of temperaturefor composite p-channel 33 of Si_(0.2)Ge_(0.8)/Ge when grown on aproperly relaxed Si_(0.65)Ge_(0.35) buffer layer 12, and compares it tocurve 72 which shows the degraded mobility behavior associated with apoor quality or defective composite channel structure ofSi_(0.2)Ge_(0.8)/Ge when grown on a lower content Si_(0.75)Ge_(0.25)buffer showing the sensitivity of the composite p-channel 33 to theproper design of layer 12 such as the composition profile, extent ofrelaxation, and remaining stacking faults and misfit dislocations. InFIG. 8, the ordinate represents hole mobility μ_(h) in cm²/Vs and theabscissa represents temperature in degrees K. The degraded mobilitybehavior shown by curve 72 is due to the presence of stacking faultsoccurring in the composite p-channel 33 of Si_(0.2)Ge_(0.8)/Ge, asillustrated in FIG. 7 in the case when the composite p-channel 33 isfabricated on a less relaxed or a lower Ge content epitaxial layerrelative to layer 12 of Si_(0.65)Ge_(0.35). The measured mobilities asshown by curve 71 for a Si_(0.2)Ge_(0.8)/Ge composite p-channel 33 are afactor of 6 to 7 higher than found in Si p-channel field effecttransistors. The measured mobilities as shown by curve 71 for compositep-channel 33 had a defect density similar to that shown in FIG. 6 and istypically in the range from 10⁴ to 10⁶ defects/cm². The measuredmobilities as shown by curve 72 for composite p-channel 33 had a defectdensity similar to that shown in FIG. 7 and is typically in the rangefrom 10⁶ to 10⁸ defects/cm2. At 300 K, the mobility μ_(h) of compositep-channel 33 equals 1,360 cm²/Vs at a sheet carrier density of 1.4×10¹²cm⁻². At 20 K, the mobility μ_(h) of composite p-channel 33 equals 9,800cm²/Vs at a sheet carrier density of 3.17×10¹² cm⁻².

[0052] In an alternate embodiment shown in FIG. 9, channel 43 comprisinglayers 16 and 17 are formed above buffer layer 12, SiGe layer 15 isformed above channel 43, Si layer 14 is formed above layer 15 and thesupply layer, p-doped Si_(1−x)Ge_(x) layer 13 is formed above Si layer14. A dielectric layer 81, for example, silicon dioxide is formed overSiGe layer 13. In FIG. 9, like references are used for functionscorresponding to the apparatus of FIG. 1.

[0053] In FIG. 1, either one of spacer layers, for example, Si spacerlayer 14 or SiGe spacer layer 15 may be structurally omitted from thethe composite p-channel 33 layered structure 10 without introducing anymajor degradation in the hole confinement and mobility of the carriersin p-channel 33.

[0054] In the design of a modulation-doped device 80 shown in FIG. 9, athicker spacer of spacer layers 15 and 14 is usually more desirable andimportant when attempting to optimize the carrier mobility transport atlow temperatures (i.e. less than <20 K) by further separation of theactive carriers in p-channel 43 from ionized hole donors in the supplylayer 13. Nevertheless, for room temperature transport, there is minimalobservable effect (if any at all) when only one spacer layer of eitherSi spacer layer 14 or SiGe spacer layer 15 is present to space compositechannel 43 of modulation-doped device 80 from supply layer 13.

[0055] In a modulation-doped device 80 where supply layer 13 is situatedabove active channel 43 as shown in FIG. 9, the composite p-channellayers are comprised of thin Ge layer 16 (less than the criticalthickness at interface 19 about 10 to 20 Å) and a SiGe layer 17. Gelayer 16 is first formed on layer 12C to form interface 19. Layers 16and 17 function as the channel region 43 of a the field effecttransistor. Next, spacer layers comprised of SiGe spacer layer 15 and Sispacer layer 14 are grown over channel layer 17 which functions toseparate the dopants in the above supply layer 13 from the below activechannel of layers 16 and 17. Above spacer layer 14, a p-doped SiGesupply layer 13 is formed which functions as a donor layer or supplylayer above active channel layers of 16 and 17. The germaniumcomposition and thickness for layers 16, 17, 15, 14, and 13 may be thesame or equivalent to those of like reference numbers in FIG. 1 whichshows a composite channel layered structure 10 with the SiGe supplylayer 13 below channel 33.

[0056] A plan view of a self-aligned p-type SiGe MODFET device is shownin FIG. 10. A cross section view along the line 12-12 of FIG. 10 isshown in FIG. 11. A self-aligned MODFET design is preferred to minimizethe access resistance associated with a Schottky gated device structure,and the process usually requires patterning and evaporation of the gatemetallization prior to the source/drain Ohmic metallization. A T-shapedgate is fabricated such that the gate overhang serves as a mask for thesource and drain Ohmic contact evaporation which prevents shorting ofthe source and drain Ohmic contacts to the Schottky gate footprint. Thisbasic process scheme has been reported in a publication by M. Arafa, K.Ismail, J. O. Chu, B. S. Meyerson, and I. Adesida, entitled “A 70-GHz fTlow operating bias self-aligned p-type SiGe MODFET”, IEEE Elec. Dev.Lett. vol. 17(12), December 1996, pp. 586-588 which is incorporatedherein by reference. As shown in FIG. 11, the device consists of thelayer structure described in FIG. 1, and in FIG. 11 like references areused for layers corresponding to the layers of FIG. 1. This layerstructure design describes a modulation-doped heterostructure wherebyp-type doped layer 13, which functions as the supply layer, is separatedfrom layers 16 and 17, which function as the conducting channel region,by undoped layers 14 and 15, which function as the spacer layers. InFIG. 11, field-effect transistor 100 consists of isolation region 104created by selectively removing layers 13, 14, 15, 16, 17 and 18 suchthat the conducting composite-channel region remains only in activedevice region 105. Isolation region 104 should completely surroundactive channel region 105 as shown in FIG. 10. Isolation region 104 canthen be passivated by depositing insulating material 106, such asSiO_(x), in isolation region 104 after etching. The gate structurepreferably should be T-shaped, i.e. narrow at the bottom and wide at thetop, and have the properties of a high Schottky barrier for holes, lowresistivity, and a high temperature barrier for reaction with thesubstrate. Such properties can be obtained by utilizing a multi-levelgate stack. In the preferred embodiment, the gate 107 is patterned byelectron-beam lithography using a bi-layer or tri-layer P(MMA-PMAA)resist system, and defined using lift-off of Ti/Mo/Pt/Au. In this case,gate 107 is formed on layer 18, and from bottom to top, consists of a Tilayer 108, a Mo layer 109, a Pt layer 110 and an Au layer 111. Thisprocess enables gate footprint 112 dimensions less than 0.1 μm, andsource-to-gate and drain-to-gate dimensions as small as 0.1 μm to berealized. Gate 107 should form a narrow stripe that completely dividesthe active device region into two distinct regions on either side.Self-aligned source and drain Ohmic contacts 113 and 114 can then beformed by evaporating a metal over active device region 105, such thatthe overhang section 115 of gate 107 acts as a shadow mask to avoidshorting of source and drain contacts 113 and 114 to gate 107. In thepreferred embodiment, a thin 20-30 nm-thick layer of Pt is evaporatedover active device region 105 and then silicided at T=200-400 C. to formlow resistance source and drain contacts 113 and 114.

[0057] A cross-section view of an insulating gate field-effecttransistor on a composite p-channel layer structure is shown in FIG. 12.The device consists of the layer structure described in FIG. 1, and inFIG. 12 like references are used for layers corresponding to the layersof FIG. 1. The device additionally consists of insulating layer 120,which is formed on top of SiGe layer 18. In the preferred embodimentlayer 120 consists of SiO_(x), or Si_(x)N_(y). The device furtherconsists of isolation region 121, gate 122, and source and draincontants 123 and 124, which are configured in a similar manner asdescribed in FIG. 10. In the preferred embodiment, gate 122 is formed oninsulating layer 120. After patterning of insulating sidewall regions125, gate 122 acts as a mask for the formation of self-aligned Ohmicsource and drain contacts 123 and 124.

[0058]FIG. 13 shows an SEM micrograph of a portion of a completed,self-aligned MODFET fabricated on a composite p-channel layer structuredescribed in FIG. 10 and FIG. 11. This particular device has a gatefootprint of 0.12 μm, and source-to-gate spacing of 0.15 μm.

[0059]FIGS. 14 and 15 show graphs of the high-frequency characteristicsof a self-aligned composite-channel p-MODFET at two different biasvoltages. This device utilized the design shown in FIGS. 10 and 11, andhad a gate footprint length of 0.09 μm and a gate width of 25 μm. Theelectrical results were obtained from microwave s-parameter data takenunder optimum bias conditions at frequencies ranging from 5 to 40 GHz.The effect of parasitic elements arising from the microwave pad geometryhave been removed by measuring an open-circuit pad geometry, and thende-embedding the response of the actual device geometry from the totalsystem response.

[0060]FIG. 14 shows the forward current gain, |h₂₁|², represented bydata points 126, and the maximum unilateral gain (MUG), represented bydata points 127, plotted versus frequency, f, for a drain-to-source biasvoltage of V_(ds)=−0.6 V. FIG. 15 shows the forward current gain,|h₂₁|², represented by data points 128, and the maximum unilateral gain(MUG), represented by data points 129, plotted vs. frequency for adrain-to-source bias voltage of V_(ds)=−1.5 V. The unity current gaincutoff frequency, f_(T), is obtained by extrapolating |h₂₁|² versusfrequency at −20 dB/decade until |h₂₁|² is equal to unity. Theextrapolation of data points 126, representative of |h₂₁|² atV_(ds)=−0.6 V, versus frequency is shown in FIG. 14 by solid curve 130.The extrapolation of data points 128, representative of |h₂₁|² atV_(ds)=−1.5 V, versus frequency is shown in FIG. 15 by solid curve 131.Similarly, the maximum frequency of oscillation, f_(max), is obtained byextrapolating to unity the high-frequency values of MUG at −20 dB/decadeuntil MUG is equal to unity. The extrapolation of data points 127,representative of MUG at V_(ds)=−0.6 V, versus frequency is shown inFIG. 14 by curve 122. The extrapolation of data points 129,representative of MUG at V_(ds)=−1.5 V, versus frequency is shown inFIG. 15 by curve 133. The extrapolations produce values of f_(T)=48 GHzand f_(max)=108 GHz at V_(ds)=−0.6 V, and f_(T)=46 GHz and f_(max)=116GHz at V_(ds)=−1.5 V. To the inventors' knowledge, the values of f_(max)are the highest ever obtained for a p-type field-effect transistor. Thefact that f_(max) exceeds 100 GHz at the low bias voltage of V_(ds)=−0.6V is particularly impressive. The record high-frequency performance ofthese depletion mode field effect transistor devices, and the low biasvoltages at which they were obtained, is a direct result of thehigh-mobility composite-channel layer structure, and the self-alignedT-gate device design described in FIGS. 10-11.

Having thus described our invention, what we claim as new and desire tosecure by Letters Patent is:
 1. A layered structure for formingp-channel field effect transistors comprising: a single crystallinesubstrate, a first layer of relaxed Si_(1−x)Ge_(x) formed epitaxially onsaid substrate where Ge fraction x is in the range from 0.35 to 0.5, asecond layer of Si_(1−x)Ge_(x) formed epitaxially on said first layer, athird layer of undoped Si formed epitaxially on said second layer, afourth layer of undoped Si_(1−x)Ge_(x) formed epitaxially on said thirdlayer, a fifth layer of Ge formed epitaxially on said fourth layerwhereby said fifth layer is under compressive strain and has a thicknessless than its critical thickness with respect to said first layer, asixth layer of Si_(1−w)Ge_(w) formed epitaxially on said fifth layerwhere the Ge fraction w is in the range from 0.5 to <1.0 and wherew-x>0.2 whereby said sixth layer is under compressive strain, and aseventh layer of Si_(1−x)Ge_(x) formed epitaxially on said sixth layer.2. The layered structure of claim 1 further including an over-shootlayer, Si_(1−y)Ge_(y), within the strain relief structure of said firstlayer having a Ge fraction y, where y=x+z and z is in the range from0.01 to 0.1, and having a thickness less than its critical thicknesswith respect to said first layer.
 3. The layered structure of claim 1wherein an active device region is a buried composite channel structuremade up of an epitaxial Ge channel of said fifth layer and an epitaxialSi_(1−w)Ge_(w) channel of said sixth layer having a higher compressivestrain to provide a deeper quantum well or a higher barrier for betterhole confinement as compared to a single layer channel device alone. 4.The layered structure of claim 1 wherein said fifth layer is formed attemperatures where 3D growth of Ge films does not occur to generateinterface roughness problems and at a temperature range from 275°-350°C. where 2D growth of Ge films does occur.
 5. The layered structure ofclaim 1 wherein the Ge content w may be graded within said sixth layerstarting with a higher Ge content nearer said fifth layer and gradingdown in Ge content towards the upper surface of said sixth layer.
 6. Thelayered structure of claim 1 wherein a spacer region comprises saidthird layer of strained Si and said fourth layer of relaxedSi_(1−x)Ge_(x).
 7. The layered structure of claim 1 wherein said thirdlayer is under tensile strain and is commensurate having a thicknessbelow its critical thickness with respect to said first layer at itsinterface with said second layer.
 8. The layered structure of claim 1wherein said second layer is a p-doped Si_(1−x)Ge_(x) layer formed belowa channel region of said fifth and sixth layers and separated therefromby said third layer of Si and said fourth layer of Si_(1−x)Ge_(x), saidsecond layer is to having a thickness in the range from 1 to 20 nm witha preferred thickness from 4 to 5 nm and having an electrically activedonor dose in the range from 1 to 3×10¹² cm⁻².
 9. A layered structurefor forming p-channel field effect transistors comprising: a singlecrystalline substrate, a first layer of relaxed Si_(1−x)Ge_(x) formedepitaxially on said substrate where Ge fraction x is in the range from0.35 to 0.5, a second layer of Si_(1−x)Ge_(x) formed epitaxially on saidfirst layer, a third layer of undoped Si formed epitaxially on saidsecond layer, a fourth layer of Ge formed epitaxially on said thirdlayer whereby said fourth layer is under compressive strain and having athickness less than its critical thickness with respect to said firstlayer, a fifth layer of Si_(1w)Ge_(w) formed epitaxially on said fourthlayer wherein the Ge fraction w is in the range from 0.5 to <1.0 andwhere w-x>0.2 whereby said fifth layer is under compressive strain, anda sixth layer of Si_(1−x)Ge_(x) formed epitaxially on said fifth layer.10. The layered structure of claim 9 further including an over-shootlayer, Si_(1−y)Ge_(y), within the strain relief structure of said firstlayer having a Ge fraction y, where y=x+z and z is in the range from0.01 to 0.1, and having a thickness less than its critical thicknesswith respect to said first layer.
 11. The layered structure of claim 9wherein an active device region is a buried composite channel structuremade up of an epitaxial Ge channel of said fourth layer and an epitaxialSi_(1−w)Ge_(w) channel of said fifth layer having a higher compressivestrain to provide a deeper quantum well or a higher barrier for betterhole confinement as compared to a single layer channel device alone. 12.The layered structure of claim 9 wherein said fourth layer is formed attemperatures where 3D growth of Ge films does not occur to generateinterface roughness problems and at a temperature range from 275°-350°C. where 2D growth of Ge films does occur.
 13. The layered structure ofclaim 9 wherein the Ge content w may be graded within said fifth layerstarting with a higher Ge content nearer said fourth layer and gradingdown in Ge content towards the upper surface of said fifth layer. 14.The layered structure of claim 9 wherein a spacer region is a singlelayer structure comprised of said third layer wherein said third layeris strained Si.
 15. The layered structure of claim 9 wherein said thirdlayer is under tensile strain and is commensurate having a thicknessbelow its critical thickness with respect to said first layer at itsinterface with said second layer.
 16. The layered structure of claim 9wherein said third layer Si may be substituted with a relaxedSi_(1−x)Ge_(x) layer with an adjustable thickness to allow the spacerthickness to be varied accordingly whereby the supply dose may beoptimized for device applications as a function of temperature in therange from 0.4 to 425 K.
 17. The layered structure of claim 9 whereinsaid second layer is a p-doped Si_(1−x)Ge_(x) layer formed below achannel region of said fourth and fifth layers and separated therefromby said third layer of Si.
 18. The layered structure of claim 16 whereinthe supply layer of said second layer is formed and separated below thechannel region of said fourth and fifth layers by said relaxedSi_(1−x)Ge_(x) layer.
 19. A layered structure for forming p-channelfield effect transistors comprising: a single crystalline substrate, afirst layer of relaxed Si_(1−x)Ge_(x) formed epitaxially on saidsubstrate where Ge fraction x is the range from 0.35 to 0.5, a secondlayer of Ge formed epitaxially on said first layer whereby said secondlayer is under compressive strain and having a thickness less than itscritical thickness with respect to said first layer, a third layer ofSi_(1−w)Ge_(w) formed epitaxially on said second layer where the Gefraction w is in the range from 0.5 to <1.0 and where w-x>0.2 wherebysaid third layer is under compressive strain, a fourth layer of undopedSi_(1−x)Ge_(x) formed epitaxially on said third layer, a fifth layer ofundoped Si form ed epitaxially on said fourth layer, and a sixth layerof p-doped Si_(1−x)Ge_(x) formed epitaxially on said fifth layer. 20.The layered structure of claim 19 further including an over-shoot layer,Si_(1−y)Ge_(y), within the strain relief structure of said first layerhaving a Ge fraction y, where y=x+z and z is in the range from 0.01 to0.1, and having a thickness less than its critical thickness withrespect to said first layer.
 21. The layered structure of claim 19wherein an active device region is a buried composite channel structuremade up of an epitaxial Ge channel of said second layer and an epitaxialSi_(1−w)Ge_(w) channel of said third layer having a higher compressivestrain to provide a deeper quantum well or a higher barrier for betterhole confinement as compared to a single layer channel device alone. 22.The layered structure of claim 19 wherein said second layer is formed attemperatures where 3D growth of Ge films does not occur to generateinterface roughness problems and at a temperature range from 275°-350°C. where 2D growth of Ge films does occur.
 23. The layered structure ofclaim 19 wherein the Ge content w may be graded within said third layerstarting with a higher content nearer said second layer and grading downin Ge content towards the upper surface of said third layer.
 24. Thelayered structure of claim 19 wherein a spacer region is a compositelayer structure comprising said fifth layer of strained Si and saidfourth layer of relaxed Si_(1−x)Ge_(x).
 25. The layered structure ofclaim 19 wherein said fifth layer is under tensile strain and iscommensurate having a thickness below its critical thickness withrespect to said first layer at its interface with said second layer. 26.The layered structure of claim 19 wherein the supply layer is a p-dopedSi_(1−x)Ge_(x) layer of said sixth layer formed above a channel regionof said second and third layers and is separated by a composite spacerstructure of said fifth layer of Si and said fourth layer ofSi_(1−x)Ge_(x).
 27. A layered structure for forming p-channel fieldeffect transistors comprising: a single crystalline substrate, a firstlayer of relaxed Si_(1−x)Ge_(x) formed epitaxially on said substratewhere Ge fraction x is the range from 0.35 to 0.5, a second layer of Geformed epitaxially on said first layer whereby said second layer isunder compressive strain and has a thickness less than its criticalthickness with respect to said first layer, a third layer ofSi_(1−x)Ge_(x) formed epitaxially on said second layer where the Gefraction w is in the range from 0.5 to <1.0 and where w-x>0.2 wherebysaid third layer is under compressive strain, a fourth layer of undopedSi_(1−x)Ge_(x) formed epitaxially on said third layer, and a fifth layerof p-doped Si_(1−x)Ge_(x) formed epitaxially on said fourth layer. 28.The layered structure of claim 27 further including an over-shoot layer,Si_(1−y)Ge_(y), within the strain relief structure of said first layerhaving a Ge fraction y, where y=x+z and z is in the range from 0.01 to0.1, and having a thickness less than its critical thickness withrespect to said first layer.
 29. The layered structure of claim 27wherein an active device region is a buried composite channel structuremade up of an epitaxial Ge channel of said second layer and an epitaxialSi_(1−w)Ge_(w) channel of said third layer having a higher compressivestrain to provide a deeper quantum well or a higher barrier for betterhole confinement as compared to a single layer channel device alone. 30.The layered structure of claim 27 wherein said second layer is formed attemperatures where 3D growth of Ge films does not occur to generateinterface roughness problems and at a temperature range from 275°-350°C. where 2D growth of Ge films does occur.
 31. The layered structure ofclaim 27 wherein the Ge content w may be graded within said third layerstarting with a higher content nearer said second layer and grading downin Ge content towards the upper surface of said third layer.
 32. Thelayered structure of claim 27 wherein a spacer region is a single layerstructure comprised of a relaxed Si_(1−x)Ge_(x) layer of said fourthlayer.
 33. The layered structure of claim 27 wherein said fourth layerof Si_(1−x)Ge_(x) may be substituted with a thin strained commensurateSi layer whereby a thin spacer thickness may be provided for a MODFETdevice.
 34. The layered structure of claim 27 wherein said fifth layeris a p-doped Si_(1−x)Ge_(x) layer formed above a channel region of saidsecond and third layers and separated therefrom by said fourth layer ofSi_(1−x)Ge_(x).
 35. The layered structure of claim 33 wherein said fifthlayer is a p-doped Si_(1−x)Ge_(x) layer formed above a channel region ofsaid second and third layers and separated therefrom by a thin strainedcommensurate Si layer.
 36. A field-effect transistor structureconsisting of the layered structure of claim 1, further comprising,electrical isolation regions created by the selective removal of atleast said seventh through second layer, a Schottky gate electrodeformed on said seventh layer, a source electrode located on one side ofsaid gate electrode, and a drain electrode located on the other side ofsaid gate electrode.
 37. A field-effect transistor structure consistingof the layered structure of claim 9, further comprising, electricalisolation regions created by the selective removal of at least saidsixth through second layer, a Schottky gate electrode formed on saidsixth layer, a source electrode located on one side of said gateelectrode, and a drain electrode located on the other side of said gateelectrode.
 38. A field-effect transistor structure consisting of thelayered structure of claim 1, further comprising, electrical isolationregions created by the selective removal of at least said sevenththrough second layer, a gate dielectric formed on said seventh layer, agate electrode on said gate dielectric, a source electrode located onone side of said gate electrode, and a drain electrode located on theother side of said gate electrode.
 39. A field-effect transistorstructure consisting of the layered structure of claim 9, furthercomprising, electrical isolation regions created by the selectiveremoval of at least said sixth through second layer, a gate dielectricformed on said sixth layer, a gate electrode on said gate dielectric, asource electrode located on one side of said gate electrode, and a drainelectrode located on the other side of said gate electrode.
 40. Afield-effect transistor structure consisting of the layered structure ofclaim 19, further comprising, electrical isolation regions created bythe selective removal of at least said sixth through second layer, agate dielectric formed on said sixth layer, a gate electrode on saidgate dielectric, a source electrode located on one side of said gateelectrode, and a drain electrode located on the other side of said gateelectrode.
 41. A field-effect transistor structure consisting of thelayered structure of claim 27, further comprising, electrical isolationregions created by the selective removal of at least said fifth throughsecond layer, a gate dielectric formed on said fifth layer, a gateelectrode on said gate dielectric, a source electrode located on oneside of said gate electrode, and a drain electrode located on the otherside of said gate electrode.
 42. A layered structure for formingelectrical devices thereon comprising: a single crystalline substrate, afirst layer of relaxed Si_(1−x)Ge_(x) formed epitaxially on saidsubstrate where Ge fraction x is in the range from 0.35 to 0.5, anover-shoot layer, Si_(1−y)Ge_(y), within the relaxed structure of saidfirst layer having a Ge fraction y, where y=x+z and z is in the rangefrom 0.01 to 0.1, and having a thickness less than its criticalthickness with respect to the top of said first layer, and a secondlayer of Si_(1−x)Ge_(x) formed epitaxially on said first layer.
 43. Amethod for forming p-channel field effect transistors comprising thesteps of: selecting a single crystalline substrate, forming a firstlayer of relaxed Si_(1−x)Ge_(x) formed epitaxially on said substratewhere Ge fraction x is in the range from 0.35 to 0.5, forming a secondlayer of Si_(1−x)Ge_(x) epitaxially on said first layer, forming a thirdlayer of undoped Si f epitaxially on said second layer, forming a fourthlayer of undoped Si_(1−x)Ge_(x) f epitaxially on said third layer,forming a fifth layer of Ge epitaxially on said fourth layer wherebysaid fifth layer is under compressive strain and has a thickness lessthan its critical thickness with respect to said first layer, forming asixth layer of Si_(1−w)Ge_(w) epitaxially on said fifth layer where theGe fraction w is in the range from 0.5 to <1.0 and where w-x>0.2 wherebysaid sixth layer is under compressive strain, and forming a seventhlayer of Si_(1−x)Ge_(x) epitaxially on said sixth layer.
 44. The methodof claim 43 further including the steps of forming an over-shoot layer,Si_(1−y)Ge_(y), within the strain relief structure of said first layerhaving a Ge fraction y, where y=x+z and z is in the range from 0.01 to0.1, and having a thickness less than its critical thickness withrespect to said first layer.
 45. The method of claim 43 wherein saidfifth layer is formed at temperatures where 3D growth of Ge films doesnot occur to generate interface roughness problems and at a temperaturerange from 275°-350° C. where 2D growth of Ge films does occur.
 46. Themethod of claim 43 wherein said step of forming a sixth layer includesthe step of grading the Ge content w within said sixth layer startingwith a higher Ge content nearer said fifth layer and grading down in Gecontent towards the upper surface of said sixth layer.
 47. The layeredstructure of claim 43 wherein said second layer is a p-dopedSi_(1−x)Ge_(x) layer formed below a channel region of said fifth andsixth layers and separated therefrom by said third layer of Si and saidfourth layer of Si_(1−x)Ge_(x), said second layer is to having athickness in the range from 1 to 20 nm with a preferred thickness from 4to 5 nm and having an electrically active donor dose in the range from 1to 3×10¹² cm⁻².
 48. A method for forming p-channel field effecttransistors comprising: selecting a single crystalline substrate,forming a first layer of relaxed Si_(1−x)Ge_(x) epitaxially on saidsubstrate where Ge fraction x is in the range from 0.35 to 0.5, forminga second layer of Si_(1−x)Ge_(x) f epitaxially on said first layer,forming a third layer of undoped Si f epitaxially on said second layer,forming a fourth layer of Ge epitaxially on said third layer wherebysaid fourth layer is under compressive strain and having a thicknessless than its critical thickness with respect to said first layer,forming a fifth layer of Si_(1w)Ge_(w) epitaxially on said fourth layerwherein the Ge fraction w is in the range from 0.5 to <1.0 and wherew-x>0.2 whereby said fifth layer is under compressive strain, andforming a sixth layer of Si_(1−x)Ge_(x) epitaxially on said fifth layer.49. The method of claim 48 further including the step of forming anover-shoot layer, Si_(1−y)Ge_(y), within the strain relief structure ofsaid first layer having a Ge fraction y, where y=x+z and z is in therange from 0.01 to 0.1, and having a thickness less than its criticalthickness with respect to said first layer.
 50. The layered structure ofclaim 48 wherein said fourth layer is formed at temperatures where 3Dgrowth of Ge films does not occur to generate interface roughnessproblems and at a temperature range from 275°-350° C. where 2D growth ofGe films does occur.
 51. The layered structure of claim 48 wherein saidstep of forming a sixth layer includes the step of grading the Gecontent w may be graded within said fifth layer starting with a higherGe content nearer said fourth layer and grading down in Ge contenttowards the upper surface of said fifth layer.
 52. The method of claim48 wherein said third layer Si may be substituted with a relaxedSi_(1−x)Ge_(x) layer with an adjustable thickness to allow the spacerthickness to be varied accordingly whereby the supply dose may beoptimized for device applications as a function of temperature in therange from 0.4 to 425 K.
 53. The method of claim 48 wherein said secondlayer of p-doped Si_(1−x)Ge_(x) layer is formed below a channel regionof said fourth and fifth layers and separated therefrom by said thirdlayer of Si.
 54. The method of claim 52 wherein the supply layer of saidsecond layer is formed and separated below the channel region of saidfourth and fifth layers by said relaxed Si_(1−x)Ge_(x) layer.
 55. Amethod for forming p-channel field effect transistors comprising:selecting a single crystalline substrate, forming a first layer ofrelaxed Si_(1−x)Ge_(x) epitaxially on said substrate where Ge fraction xis the range from 0.35 to 0.5, forming a second layer of Ge epitaxiallyon said first layer whereby said second layer is under compressivestrain and having a thickness less than its critical thickness withrespect to said first layer, forming a third layer of Si_(1−w)Ge_(w) fepitaxially on said second layer where the Ge fraction w is in the rangefrom 0.5 to <1.0 and where w-x>0.2 whereby said third layer is undercompressive strain, forming a fourth layer of undoped Si_(1−x)Ge_(x)epitaxially on said third layer, forming a fifth layer of undoped Siepitaxially on said fourth layer, and forming a sixth layer of p-dopedSi_(1−x)Ge_(x) epitaxially on said fifth layer.
 56. The method of claim55 further including an over-shoot layer, Si_(1−y)Ge_(y) within thestrain relief structure of said first layer having a Ge fraction y,where y=x+z and z is in the range from 0.01 to 0.1, and having athickness less than its critical thickness with respect to said firstlayer.
 22. The layered structure of claim 19 wherein said second layeris formed at temperatures where 3D growth of Ge films does not occur togenerate interface roughness problems and at a temperature range from275°-350° C. where 2D growth of Ge films does occur.
 57. The method ofclaim 55 wherein said second layer is formed at temperatures where 3Dgrowth of Ge films does not occur to generate interface roughnessproblems and at a temperature range from 275°-350° C. where 2D growth ofGe films does occur.
 58. The layered structure of claim 55 wherein saidstep of forming a third layer includes the step of grading the Gecontent w within said third layer starting with a higher content nearersaid second layer and grading down in Ge content towards the uppersurface of said third layer.
 59. The method of claim 55 wherein thesupply layer of p-doped Si_(1−x)Ge_(x) layer of said sixth layer isformed above a channel region of said second and third layers and isseparated by a composite spacer structure of said fifth layer of Si andsaid fourth layer of Si_(1−x)Ge_(x).
 60. A method for forming p-channelfield effect transistors comprising: selecting a single crystallinesubstrate, forming a first layer of relaxed Si_(1−x)Ge_(x) epitaxiallyon said substrate where Ge fraction x is the range from 0.35 to 0.5,forming a second layer of Ge epitaxially on said first layer wherebysaid second layer is under compressive strain and has a thickness lessthan its critical thickness with respect to said first layer, forming athird layer of Si_(1−w)Ge_(w) f epitaxially on said second layer wherethe Ge fraction w is in the range from 0.5 to <1.0 and where w-x>0.2whereby said third layer is under compressive strain, forming a fourthlayer of undoped Si_(1−x)Ge_(x) epitaxially on said third layer, and afifth layer of p-doped Si_(1−x)Ge_(x) formed epitaxially on said fourthlayer.
 61. The method of claim 60 further including the step of formingan over-shoot layer, Si_(1−y)Ge_(y), within the strain relief structureof said first layer having a Ge fraction y, where y=x+z and z is in therange from 0.01 to 0.1, and having a thickness less than its criticalthickness with respect to said first layer.
 62. The method of claim 60wherein said second layer is formed at temperatures where 3D growth ofGe films does not occur to generate interface roughness problems and ata temperature range from 275°-350° C. where 2D growth of Ge films doesoccur.
 63. The method of claim 60 wherein said step of forming a thirdlayer includes the step of grading the Ge content w within said thirdlayer starting with a higher content nearer said second layer andgrading down in Ge content towards the upper surface of said thirdlayer.
 64. The method of claim 60 wherein said fifth layer is a p-dopedSi_(1−x)Ge_(x) layer formed above a channel region of said second andthird layers and separated therefrom by said fourth layer ofSi_(1−x)Ge_(x).
 65. The layered structure of claim 60 wherein said fifthlayer is a p-doped Si_(1−x)Ge_(x) layer formed above a channel region ofsaid second and third layers and separated therefrom by a thin strainedcommensurate Si layer.
 66. A method of forming a field-effect transistorstructure consisting of the method of claim 43, further comprising thesteps of, forming electrical isolation regions by the selective removalof at least said seventh through second layer, forming a Schottky gateelectrode on said seventh layer, forming a source electrode located onone side of said gate electrode, and forming a drain electrode locatedon the other side of said gate electrode.
 67. A method for forming afield-effect transistor structure consisting of the method of claim 48,further comprising the steps of, forming electrical isolation regions bythe selective removal of at least said sixth through second layer,forming a Schottky gate electrode on said sixth layer, forming a sourceelectrode located on one side of said gate electrode, and forming adrain electrode located on the other side of said gate electrode.
 68. Amethod of forming a field-effect transistor structure consisting of themethod of claim 1, further comprising, forming electrical isolationregions by the selective removal of at least said seventh through secondlayer, forming a gate dielectric on said seventh layer, forming a gateelectrode on said gate dielectric, forming a source electrode located onone side of said gate electrode, and forming drain electrode located onthe other side of said gate electrode.
 69. A method of forming afield-effect transistor structure consisting of the method of claim 48,further comprising the steps of, forming electrical isolation regions bythe selective removal of at least said sixth through second layer,forming a gate dielectric f on said sixth layer, forming a gateelectrode on said gate dielectric, forming a source electrode located onone side of said gate electrode, and forming drain electrode located onthe other side of said gate electrode.
 70. A method for forming afield-effect transistor structure consisting of the method of claim 55,further comprising, forming electrical isolation regions by theselective removal of at least said sixth through second layer, forming agate dielectric on said sixth layer, forming a gate electrode on saidgate dielectric, forming a source electrode located on one side of saidgate electrode, and forming a drain electrode located on the other sideof said gate electrode.
 71. A method of forming a field-effecttransistor structure consisting of the method of claim 60, furthercomprising, forming electrical isolation regions by the selectiveremoval of at least said fifth through second layer, forming a gatedielectric formed on said fifth layer, forming a gate electrode on saidgate dielectric, forming a source electrode located on one side of saidgate electrode, and forming a drain electrode located on the other sideof said gate electrode.
 72. A method for forming electrical devicescomprising the steps of: forming a single crystalline substrate, forminga first layer of relaxed Si_(1−x)Ge_(x) formed epitaxially on saidsubstrate where Ge fraction x is in the range from 0.35 to 0.5, formingan over-shoot layer, Si_(1−y)Ge_(y), within the relaxed structure ofsaid first layer having a Ge fraction y, where y=x+z and z is in therange from 0.01 to 0.1, and having a thickness less than its criticalthickness with respect to the top of said first layer, and forming asecond layer of Si_(1−x)Ge_(x) formed epitaxially on said first layer.